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1 ? fn6164.2 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2006, 2007. all rights reserved all other trademarks mentioned are the property of their respective owners. ISL51002 10-bit video analog fr ont end (afe) with measurement and auto-adjust features the ISL51002 3-channel, 10-bit analog front end (afe) contains all the functionality needed to digitize analog ypbpr video from hdtv tuners, settop boxes, sd and hd dvds, as well as rgb graphics signals from personal computers and workstations. the fourth generation analog design delivers 10-bit performance and a 165msps maximum conversion rate supporting reso lutions up to 1080p/uxga at 60hz. the front end's programmable input bandwidth ensures sharp, low noise images at all resolutions. to accelerate and simplify mode detection, the ISL51002 integrates a sophisticated set of measurement tools that fully characterizes the video signal and timing, offloading the host microcontroller. automatic black level compensation (ablc?) eliminates part-to-part offset variation, ensuring perfect black level performance in every application. the ISL51002's digital pll generates a pixel clock from the analog source's hsync or sog (sync-on-green) signals. pixel clock output frequencies range from 10mhz to 165mhz with sampling clock jitter of 250ps peak to peak. applications ?flat panel tvs ? front/rear projection tvs ? pc lcd monitors and projectors ? high quality scan converters ? video/graphics processing features ? automatic sampling phase adjustment ? 10-bit triple analog to digital converters with oversampling up to 8x in video modes ? 165msps maximum conversion rate (ISL51002cqz-165) ? robust, glitchless macrovisi on?-compliant sync separator ? analog vcr ?trick mode? support ? ablc? for perfect black level performance ? 4 channel input multiplexer ? precision sync timing measurement ? rgb to yuv color space converter ? low pll clock jitter (250ps p-p) ? programmable input bandwidth (10mhz to 450mhz) ? 64 interpixel sampling positions ? 6db gain adjustment rate ? pb-free (rohs compliant) related literature ? technical brief tb363 ?guidelines for handling and processing moisture sensit ive surface mount devices (smds)?. simplified block diagram rgb/ypbpr in 0 pga 10-bit adc + o f f s e t d a c ablc? 10 x3 sog in 0, 1, 2, 3 hsync in 0, 1, 2, 3 vsync in 0, 1, 2, 3 sync processing digital pll voltage clamp color space converter rgb/ypbpr in 1 rgb/ypbpr in 2 rgb/ypbpr in 3 3 3 3 3 rgb/yuv out pixelclk out hs out field out hsync out /vsync out de out 2 measurement, autoadjust, afe configuration and control data sheet september 19, 2007
2 fn6164.2 september 19, 2007 block diagram ordering information part number/part marking temperature range (c) package pkg. dwg # ISL51002cqz-110 (note) 0 to +70 128 ld mqfp (pb-free) mdp0055 ISL51002cqz-150 (note) 0 to +70 128 ld mqfp (pb-free) mdp0055 ISL51002cqz-165 (note) 0 to +70 128 ld mqfp (pb-free) mdp0055 ISL51002evalz evaluation platform note: these intersil pb-free plas tic packaged products employ special pb-free mate rial sets; molding compounds/die attach materi als and 100% matte tin plate plus anneal - e3 termination finish, which is ro hs compliant and compatible with both snpb and pb-free solderin g operations. intersil pb-free products are msl classified at pb-free peak reflow temper atures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. r in 0 r in 1 pga 10-bit adc + offset dac ablc? 10 10 10 r[9:0] sog in 0,1,2,3 hsync in 0,1,2,3 vsync in 0,1,2,3 clockinv in xtal in xtal out scl sda saddr sync processing digital pll measurement, autoadjust, afe configuration and control dataclk dataclk int serial interface hsync out vsync out xclk out r in 2 r in 3 voltage clamp g in 0 g in 1 pga 10-bit adc + offset dac ablc? 10 10 10 g[9:0] g in 2 g in 3 voltage clamp b in 0 b in 1 pga 10-bit adc + offset dac ablc? 10 10 10 b[9:0] b in 2 b in 3 voltage clamp coast in clamp in extclk in fbc in hs out reset field de fbc out output data formatter color space converter ISL51002
3 fn6164.2 september 19, 2007 absolute maximum rati ngs thermal information 3.3v supply voltage (v a3.3 , v d3.3 , vpll a3.3 ) . . . . . . . . . . . . . 4.6v 1.8v supply voltage (v a1.8 , v d1.8 , vadc d1.8 ). . . . . . . . . . . . . 2.5v voltage on any input pin . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 6v output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ma esd rating human body model (per mil-std-883 method 3015.7) . . .3000v machine model (per eiaj ed-4701 method c-111) . . . . . . . .300v charged device model (per eos/esd ds5.3, 4/14/93) . . .1000v operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . 0c to +70c supply voltage range . . . . . . . . . . . . . . . . . 3.3v 10%, 1.8v 10% thermal resistance (typical) ja (c/w) jc (c/w) mqfp package (notes 1, 2) . . . . . . . . 30 16 maximum power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2w maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . +125c maximum storage temperature range . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. ja is measured with the component mounted on a low effective therma l conductivity test board in free air. see tech brief tb379 fo r details. 2. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications specifications apply for v a3.3 = v d3.3 = v plla3.3 = 3.3v, v a1.8 = v d1.8 = v plld1.8 = v adcd1.8 = 1.8v, pixel rate = 110mhz for ISL51002-110, 150mhz for ISL51002-150, 165mhz for ISL51002-165, f xtal = 25mhz, and t a = +0c to +70c, unless otherwise specified. symbol parameter test level or notes min (note 6) typ max (note 6) units full channel characteristics conversion rate ISL51002-110 10 110 mhz ISL51002-150 10 150 mhz ISL51002-165 10 165 mhz adc resolution 10 bits missing codes guaranteed monotonic none dnl (full-channel) differential non-linearity (note 3) ISL51002-110 -0.99 0.5 +1.2 lsb ISL51002-150 -0.99 0.7 +1.3 lsb ISL51002-165 -0.99 0.8 +1.4 lsb inl (full-channel) integral non-linearity (note 3) ISL51002-110 1.9 3.6 lsb ISL51002-150 2.0 3.8 lsb ISL51002-165 2.6 4.0 lsb gain adjustment range 6 db gain adjustment resolution 10 bits gain matching between channels percent of full scale 2 % full channel offset error, ablc? enabled adc lsbs, over time and temperature 0.5 3.0 lsb offset adjustment range (ablc? enabled or disabled) (see ablc? applications information section) 50% adc fullscale analog video input characteristics (r in 0-3, g in 0-3, b in 0-3) input range 0.35 0.7 2.2 v p-p input bias current dc restore clamp off 0.01 1 a ISL51002
4 fn6164.2 september 19, 2007 input capacitance 5pf full power bandwidth programmable 10 to 450 mhz sog input characteristics (sog in 0-3) sync tip clamp 600 mv sog pull down 1a v ih /v il input threshold voltage (relative to bottom of sync tip) programmable - see register listing for details 0 to 0.3 v input capacitance 5pf hsync input characteristics (hsync in 0-3) v ih /v il input threshold voltage programmable - see register listing for details 0.4 to 3.2 v hysteresis centered around threshold voltage 240 mv i input leakage current (note 4) 10 na c in input capacitance 5pf digital input characteristics (all digital input pins except scl, vsync in 0-3) v ih input high voltage 2.0 v v il input low voltage 0.8 v i input leakage current (note 4) reset has a 65k pullup to v d3.3 10 na c in input capacitance 5pf schmitt digital input characteristics (scl, vsync in 0-3) v t + low to high threshold voltage 1.45 v v t - high to low threshold voltage 0.95 v i input leakage current 10 na c in input capacitance 5pf digital output characteristics (all output pins except int and sda) v oh output high voltage, i o = 8ma 2.4 v v ol output low voltage, i o = -8ma 0.4 v digital output characteristics (int ) v ol output low voltage, i o = -8ma open-drain, with 65k pull-up to v d3.3 0.4 v digital output characteristics (sda) v ol output low voltage, i o = -4ma open-drain 0.4 v power supply requirements v a3.3 analog supply voltage, 3.3v includes vpll a3.3 3.0 3.3 3.6 v v a1.8 analog supply voltage, 1.8v 1.65 1.8 2.0 v v d3.3 digital supply voltage, 3.3v 3.0 3.3 3.6 v v d1.8 digital supply voltage, 1.8v includes vadc d1.8 , vpll d1.8 1.65 1.8 2.0 v i a3.3 analog supply current, 3.3v (note 4) 45 90 ma ipll a3.3 14 25 ma electrical specifications specifications apply for v a3.3 = v d3.3 = v plla3.3 = 3.3v, v a1.8 = v d1.8 = v plld1.8 = v adcd1.8 = 1.8v, pixel rate = 110mhz for ISL51002-110, 150mhz for ISL51002-150, 165mhz for ISL51002-165, f xtal = 25mhz, and t a = +0c to +70c, unless otherwise specified. (continued) symbol parameter test level or notes min (note 6) typ max (note 6) units ISL51002
5 fn6164.2 september 19, 2007 i a1.8 analog supply current, 1.8v (note 4) includes 1.8v adc reference current draw 270 375 ma i d3.3 digital supply current, 3.3v (note 4) grayscale ramp input 30 60 ma i d1.8 digital supply current, 1.8v (note 4) grayscale ramp input 65 95 ma iadc d1.8 33 65 ma ipll d1.8 1.8 10 ma p d total power dissipation grayscale ramp input standby mode 0.98 1.25 w 50 100 mw ac timing characteristics pll jitter (note 5) 250 450 ps p-p sampling phase steps 5.6 per step 64 sampling phase tempco 1 ps/c sampling phase differential nonlinearity degrees out of +360 3 hsync frequency range 10 150 khz f xtal crystal frequency range 12 25 27 mhz t setup data valid before rising edge of dataclk 20pf dataclk load, 20pf data load 1.8 ns t hold data valid after rising edge of dataclk 20pf dataclk load, 20pf data load 3.4 ns notes: 3. linearity tested at room temperature and guaranteed across come rcial temperature range by correlation to characterization. 4. supply current specified at max pixel rate (165mhz) with gray scale video applied. 5. jitter tested at rated frequencies (165mhz, 150m hz, 110mhz) and at minimum frequency (10mhz). 6. parts are 100% tested at +25c. over-temperature limits established by characteriza tion and are not production tested. electrical specifications specifications apply for v a3.3 = v d3.3 = v plla3.3 = 3.3v, v a1.8 = v d1.8 = v plld1.8 = v adcd1.8 = 1.8v, pixel rate = 110mhz for ISL51002-110, 150mhz for ISL51002-150, 165mhz for ISL51002-165, f xtal = 25mhz, and t a = +0c to +70c, unless otherwise specified. (continued) symbol parameter test level or notes min (note 6) typ max (note 6) units ISL51002
6 fn6164.2 september 19, 2007 timing diagrams data output setup and hold timing rgb output data timing and latency yuv output data timing and latency pixel data dataclk t hold t setup dataclk programmable width and polarity analog video in p 1 p 2 p 3 p 4 p 5 p 6 p 7 p 8 p 0 p 9 d 0 r/g/b[9:0] hs out 8 dataclk pipeline latency p 10 p 11 p 12 d 1 d 2 d 3 hsync in the hsync edge (programm able leading or trailing) that the dpll is locked to. the sampling phase setting determines its relative position to the rest of the afe?s output signals dataclk programmable width and polarity analog video in p 1 p 2 p 3 p 4 p 5 p 6 p 7 p 8 p 0 p 9 hs out 8 dataclk pipeline latency p 10 p 11 p 12 hsync in the hsync edge (programmable leading or trailing) that the dpll is locked to. the sampling phase setting determines its relative position to the rest of the afe?s output signals dataclk g 0 (y o ) g 1 (y 1 )g 2 (y 2 ) b 0 (u o )r 0 (v 0 )b 2 (u 2 ) g[9:0] r[9:0] b[9:0] g 3 (y 3 ) r 2 (v 2 ) ISL51002
7 fn6164.2 september 19, 2007 pin configuration (mqfp, ISL51002) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 37 34 35 36 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 v a1.8 gnd a r in 3 g in 3 sog in 1 b in 3 fbc in vsync in 3 vsync in 1 vpll d1.8 gnd d xclk out saddr sda scl b7 b6 b5 b4 b3 b2 b1 b0 gnd d v d3.3 gnd d v d1.8 g7 g6 g5 g4 g3 g2 g1 g0 gnd d v d3.3 gnd d v d1.8 r7 r6 r5 r4 r3 r2 r1 r0 dataclk v d3.3 hs out hsync out vsync out gnd d gnd d v d3.3 r9 r8 g9 g8 b9 b8 gnd a v a1.8 vref green r in 2 g in 2 b in 2 gnd a v a1.8 gnd a v a3.3 r in 1 g in 1 b in 1 r in 0 g in 0 b in 0 sog in 0 sog in 2 sog in 3 atest1 clockinv in clamp in coast in de field vadc d1.8 gnd d vsync in 0 fbc out dtest1 dtest2 extclk in dtest4 dtest3 atest2 gnd a gnd a vref red v a3.3 gnd d v d1.8 hsync in 3 hsync in 1 hsync in 2 hsync in 0 vpll a3.3 gnd a xtal in xtal out reset dataclk int gnd d v d1.8 v a3.3 vref blue gnd d gnd d gnd d gnd d gnd d gnd d gnd d vsync in 2 ISL51002cqz-xxx gnd a nc nc ISL51002
8 fn6164.2 september 19, 2007 pin descriptions symbol description r in 0, 1, 2, 3 analog inputs. red channels. ac couple through 0.1f. g in 0, 1, 2, 3 analog inputs. green channels. ac couple through 0.1f. b in 0, 1, 2, 3 analog inputs. blue channels. ac couple through 0.1f. vref red , vref green , vref blue analog inputs. reference voltage for adcs. tie to 1.8v reference voltage (v a1.8 is acceptable if low noise). decouple with 0.1f capacitor to gnd a . sog in 0, 1, 2, 3 analog inputs. sync on green. connect to corres ponding green channel video source through a 0.01f capacitor in series with a 500 resistor. hsync in 0, 1, 2, 3 digital high impedance 3.3v inputs with 240mv hysteresis. connect to corresponding channel's hsync source. for 5v signals divide input with a 1k/1.9k divider . place the divider as clos e as possible to the device pin. place a 50pfcapacitor in parallel with the 1k resistor to r educe the filtering effect of the divider. vsync in 0, 1, 2, 3 digital high impedance 3.3v inputs with 240mv hysteresis. connect to corresponding channel's vsync source. for 5v signals divide input with a 1k/1 .9k divider. place the divider as close as possible to the dev ice pin. place a 50pf capacitor in parallel with the 1k resistor to r educe the filtering effect of the divider. coast in digital 3.3v input. when this input is hi gh and external coast is selected, the pll will coast, ignori ng all transistions on the active channel?s hsync/sog. clamp in digital 3.3v input.when this input is hi gh and external clamp is selected, connects the selected channels inputs to the clamp dac. clockinv in digital 3.3v input. when high, changes the pixel sampling phase by 180. toggle at frame rate during vsync to allow 2x undersampling to sample odd and even pi xels on sequential frames. tie to d gnd if unused. fbc in digital 3.3v input.connect to the fast blank signal of a scart connector. fbc out 3.3v digital output. a delayed version of the fbc in signal, aligned with the digital pixel data. reset digital 3.3v input, active low, 70k pullup to v d . take low for at least 1s and then high again to reset the ISL51002. this pin is not necessary for normal use and may be tied directly to the v d supply. xtal in analog input. connect to external 12mhz to 27mhz crystal and load capacito r (see crystal spec for recommended loading). typical oscillation amplitude is 1.0v p-p centered around 0.5v. xtal out analog output. connect to external 12mhz to 27mhz crys tal and load capacitor (see crystal spec for recommended loading). typical oscillation amplitude is 1.0v p-p centered around 0.5v. xclk out 3.3v digital output. buffered crystal clock output at f xtal or f xtal /2. may be used as syste m clock for other system components. saddr digital 3.3v input. address = 0x98 (1001100x) when tied low. address = 0 x 9a (1001101x) when tied high. scl digital input, 5v tolerant, 500mv hysteresis. serial data clock for 2-wire interface. sda bidirectional digital i/o, open drain, 5v to lerant. serial data i/o for 2-wire interface. extclk in digital 3.3v input. exter nal clock input for afe. r[9:0] 3.3v digital output. 10-bit red channel pixel data. g[9:0] 3.3v digital output. 10-bit green channel pixel data. b[9:0] 3.3v digital output. 10-bit blue channel pixel data. dataclk 3.3v digital output. data (pixel) clock output. dataclk 3.3v digital output. inverse of dataclk. hs out 3.3v digital output. hsync output aligned with pixel data. use th is output to frame the digital output data. this output is always purely horizontal sync (wit hout any composite sync signals) hsync out 3.3v digital output. buffered hsync (or sog or csync) output. this is typically used for measuring hsync period. this output will pass composite sync signals and macrovision signals if present on hsync in or sog in . vsync out 3.3v digital output. buffered vsync output. for composite sync signals, this output will be asserted for the duration of the disruption of the normal hsync pattern. this is typically used for measuring vsync period. ISL51002
9 fn6164.2 september 19, 2007 int digital output, open drain, 5v tolerant. interrupt output i ndicating mode change or command execution status. pull high with a 4.7k resistor. de 3.3v digital output. high when there is valid video data, low during horizontal and vertical blanking periods. field 3.3v digital output. for interlaced video, this output will c hanges states to indicate whet her current field is even or od d. polarity is determined by configuration register. v a3.3 power supply for the analog section. connect to a 3.3v supply and bypass each pin to gnd a with 0.1f. v a1.8 power supply for the analog section. connect to a 1.8v supply and bypass each pin to gnd a with 0.1f. vpll a3.3 power supply for the analog pll section. c onnect to a 3.3v supply and bypass to gnd a with 0.1f. gnd a ground return for v a3.3 , v a1.8 , and vpll a1.8 . v d3.3 power supply for all digital i/os. connect to a 3.3v supply and bypass each pin to gnd d with 0.1f. v d1.8 power supply for digital core logic. connect to a 1.8v supply and bypass each pin to gnd d with 0.1f. vadc d1.8 power supply for the digital adc section. connect to a 1.8v supply and bypass to gnd d with 0.1f. vpll d1.8 power supply for the digital pll section. connect to a 1.8v supply and bypass to gnd d with 0.1f. gnd d ground return for v d3.3 , v d1.8 , vadc d1.8 , and vpll d1.8 . atest1, 2 for production use only. tie to gnd a . dtest1, 2, 3, 4 for production use only. tie to gnd d . nc reserved. do not connect anything to these pins. pin descriptions (continued) symbol description ISL51002
10 fn6164.2 september 19, 2007 sync flow 10 10 10 hs out dataclk data data data 165 mhz triple 10- bit afe auto adjust timing measurement activity monitor crystal oscillator 3 output formatter 10 10 10 10 10 10 de int xtal out serial i/o hsync out sog0 sog1 sog2 sog3 hsync0 hsync1 hsync2 hsync3 vsync0 vsync1 vsync2 vsync3 ch0 ch1 ch2 ch3 3 3 3 3 ch0 to ch3 select vsync select hsync/ csync from sog or hsync select auto polling vsync out extracted vsync field o/e sog slicer a sync separator digital pll coast gen. glitch filter sog slicer b hsync slicer a hsync slicer b vsync slicer a vsync slicer b interlaced mv ext. coast 10 10 10 digital offset control (if ablc enabled) 10-bit 3x3 color space converter tri-level detection trilevel interrupt generation mask mask decimator active video signal path color key: active sync signal path monitoring/ support analog signal digital signal ISL51002
11 fn6164.2 september 19, 2007 register listing address register (default value) bits function name description status and interrupt registers 0x01 selected input channel characteristics, (read only) 1:0 sync type 00: automatic sync selection logic could not find good sync on h, v, or sog (automatic sync mode only) 01: sync on hsync/vsync 10: csync on hsync 11: csync on green channel (sog) 2 hsync polarity 0: hsync active high 1: hsync active low 3 vsync polarity 0: vsync active high 1: vsync active low 4 tri-level sync 0: bi-level sog (if sog is active) 1: tri-level sog 5 interlaced (only for csync) 0: non-interlaced or progressive signal 1: interlaced signal 6 macrovision 0: no macrovision detected 1: macrovision encoding detected 7 pll locked 0: pll unlocked 1: pll locked to incoming hsync 0x02 ch0 and ch1 activity status, (read only) 0 hsync0 activity 0: hsync0 inactive 1: hsync0 active ? there is a periodic signal with frequency >1khz and consistent low/high times on this input 1 vsync0 activity 0: vsync0 inactive 1: vsync0 active ? there is a periodic signal with frequency >20hz and consistent low/hi gh times on this input 3:2 sog0 activity 00: sog0 inactive ? no transitions detected at the sog slicer output. 01: sog0 active ? non-periodi c transitions detected at the sog slicer output ? possibly valid sog with a bad slicer threshold, or simply video with no valid sog. 10: sog0 periodic ? there is a periodic signal with frequency >1khz and consistent low/high ti mes on this input. this is most likely a valid sog signal. 4 hsync1 activity see hsy nc0 activity description 5 vsync1 activity see vsync0 activity description 7:6 sog1 activity see sog0 activity description 0x03 ch2 and ch3 activity status, (read only) 0 hsync2 activity see hsy nc0 activity description 1 vsync2 activity see vsync0 activity description 3:2 sog2 activity see sog0 activity description 4 hsync3 activity see hsy nc0 activity description 5 vsync3 activity see vsync0 activity description 7:6 sog3 activity see sog0 activity description ISL51002
12 fn6164.2 september 19, 2007 0x04 interrupt status, write a 1 to each bit to clear it, 0xff to clear all. 0 ch0 sync changed 0: no change 1: ch0 activity or polarity changed 1 ch1 sync changed 0: no change 1: ch1 activity or polarity changed 2 ch2 sync changed 0: no change 1: ch2 activity or polarity changed 3 ch3 sync changed 0: no change 1: ch3 activity or polarity changed 4 selected input channel disrupted 0: no change 1: currently selected input channel?s hsync or vsync signal has changed (fast notification of a mode change) 5 selected input channel changed 0: no change 1: currently selected input channel?s hsync or vsync period or pulse width has settled to a new value and can be measured 6 vsync int 0: default state 1: vsync occurred 7 padj int 0: default state 1: phase adjustment function completed. 0x05 interrupt mask register, (0xff) 0 ch0 mask 0: generate interrupt if ch0 sync activity, polarity, period, or pulse width changes 1: mask ch0 interrupt 1 ch1 mask 0: generate interrupt if ch1 sync activity, polarity, period, or pulse width changes 1: mask ch1 interrupt 2 ch2 mask 0: generate interrupt if ch2 sync activity, polarity, period, or pulse width changes 1: mask ch2 interrupt 3 ch3 mask 0: generate interrupt if ch3 sync activity, polarity, period, or pulse width changes 1: mask ch3 interrupt 4 input disrupted mask 0: generate interrupt if selected input channel?s sync inputs are disrupted 1: mask input channel interrupt 5 input changed mask 0: generate interrupt after selected input channel period or pulse width settles to new value 1: mask input channel interrupt 6 vsync int mask 0: generate interrupt every vsync 1: mask vsync interrupt 7 padj int mask 0: generate interrupt upon phase adjustment block request completion 1: mask phase adjustment interrupt register listing (continued) address register (default value) bits function name description ISL51002
13 fn6164.2 september 19, 2007 configuration registers 0x10 input configuration, (0x00) 1:0 input channel select sets video muxes as well as hsync, vsync, and sog input muxes. 0: ch0 1: ch1 2: ch2 (single-ended mode only) 3: ch3 (single-ended mode only) 2 differential mode enable 0: single-ended mode 1: differential mode 3 dc coupled input enable 0: ac-coupled inputs 1: dc-coupled inputs 4 rgb yuv 0: rgb inputs (clamp dac = 300mv for r, g, b, half scale analog shift for r, g, and b, base ablc target code = 0x00 for r, g, and b) 1: ypbpr inputs (clamp dac = 600mv for r and b, 300mv for g, half scale analog shift fo r g channel only, base ablc target code = 0x00 for g, = 0x80 for r and b) 5 high voltage enable 0: normal input range 1: expanded 2.2v input range 6 ext clamp sel 0: internal clamp generation 1: external clamp source 7 ext clamp pol 0: active high external clamp 1: active low external clamp 0x11 sync source selection, (0x00) 0 sync select 0: automatic (hsync, vsync sources selected based on sync activity. multiplexer se ttings chosen are displayed in the input characteristics register.) 1: manual (bits 1and 2 determine hsync and vsync source) 1 hsync source 0: hsync input pin 1: sog 2 vsync source 0: vsync input pin 1: sync separator output 0x12 red gain msb, (0x55) 7:0 red gain msb red channel gain, where: gain (v/v) = 0.5 + [9:0]/682 msb/lsb 0x00 00: gain = 0.5 v/v (1.4v p-p input = full range of adc) 0x55 00: gain = 1.0 v/v (0.7v p-p input = full range of adc) 0xff c0: gain = 2.0 v/v (0.35v p-p input = full range of adc) 0x13 red gain lsb, (0x00) 5:0 n/a 7:6 red gain lsb 2 lsbs of 10-bit gain word 0x14 green gain msb, (0x55) 7:0 green gain msb see red gain 0x15 green gain lsb, (0x00) 5:0 n/a 7:6 green gain lsb see red gain 0x16 blue gain msb, (0x55) 7:0 blue gain msb see red gain 0x17 blue gain lsb, (0x00) 5:0 n/a 7:6 blue gain lsb see red gain 0x18 red offset msb, (0x80) 7:0 red offset msb ablc off: upper 8-bits to red offset dac ablc enabled: red digital offset 0x00 00 = min dac value or -0x80 digital offset 0x80 00 = mid dac value or 0x00 digital offset, 0xff c0= max dac value or +0x7f digital offset register listing (continued) address register (default value) bits function name description ISL51002
14 fn6164.2 september 19, 2007 0x19 red offset lsb, (0x00) 5:0 n/a 7:6 red offset lsb 2 lsbs of 10-bit offset word 0x1a green offset msb, (0x80) 7:0 green offset msb ablc off: upper 8-bits to green offset dac ablc enabled: green digital offset (see red offset) 0x1b green offset lsb, (0x00) 5:0 n/a 7:6 green offset lsb see red offset 0x1c blue offset msb, (0x80) 7:0 blue offset msb ablc off: upper 8-bits to blue offset dac ablc enabled: blue digital offset (see red offset) 0x1d blue offset lsb, (0x00) 5:0 n/a 7:6 blue offset lsb see red offset 0x1e pll htotal msb, (0x06) 5:0 pll htotal msb 14-bit htotal. pll updated on lsb write only. 0x1f pll htotal lsb, (0x98) 7:0 pll htotal lsb pll updated on lsb write only. sxga default 0x20 pll phase, (0x00) 5:0 pll sampling phase used to cont rol the phase of the adc?s sample point relative to the period of a pixel. adjust to obtain optimum image quality. one step = 5.625 (1.56% of pixel period). 0x21 pll pre-coast, (0x04) 7:0 pre-coast number of lines the pll will coast prior to the start of vsync. 0x22 pll post-coast, (0x04) 7:0 post-coast number of lines the pll will coast after the end of vsync. 0x23 pll misc, (0x00) 0 pll lock edge hsync 0: pll lo cks to trailing edge of selected hsync (default) 1: pll locks to leading edge of selected hsync 1 clkinv enable 0: clkinv input ignored 1: clkinv input enabled 2 ext coast sel 0: internal coast generation 1: external coast source 3 ext coast pol 0: active high external coast 1: active low external coast 4 ext clock 0: internal pixel clock from dpll 1: external pixel clock from extclkin pin 0x24 dc restore and ablc starting pixel msb, (0x00) 5:0 dc restore and ablc starting pixel (msb) pixel after raw hsync trailing edge to begin dc restore and ablc. 14-bits. 0x25 dc restore and ablc starting pixel lsb, (0x02) 7:0 dc restore and ablc starting pixel (lsb) 0x26 dc restore clamp width, (0x10) 7:0 dc restore clamp width only applies to dc restore clamp used for ac-coupled configurations. a value of 0x00 means the clamp dac is never connected to the input. register listing (continued) address register (default value) bits function name description ISL51002
15 fn6164.2 september 19, 2007 0x27 ablc configuration, (0x40) 0 ablc disable 0: ablc on (default) - use 10-bit digital offset control. 0x000 = -0x200 lsb offset, 0x3ff = +0x1ff lsb offset, 0x200 = 0x000 lsb offset 1: ablc off - use 10-bit offset dacs, bypass digital adder (add/subtract nothing, but keep same delay through channel) 1 offset dac range 0: 1/2 adc fullscale (1 lsb = 1 adc lsbs) 1: 1/4 adc fullscale (1 lsb = 0.5 adc lsbs) 3:2 ablc pixel width number of black pixe ls averaged every line for ablc function 00: 16 pixels [default] 01: 32 pixels 10: 64 pixels 11: 128 pixels 6:4 ablc bandwidth ablc time constant (lines) = 2 ([5+6:4]) 000 = 32 lines 100 = 512 lines (default) 111 = 4096 lines 0x28 output format 1, (0x00) 0 data output format 0: 4:4:4 (24-bit/30-bit output) 1: 4:2:2 (16-bit/20-bit output on g and r) 1 4:2:2 order 0: first pixel on r channel is u 1: first pixel on r channel is v 2 4:2:2 processing 0: u, v fitered (high quality) 1: odd u, v pixels dropped (lower quality) 3 8-bit mode 0: all 10-bits of each channel active 1: 2 lsbs of each channel driv en low (in 8-bit applications, keep the lsbs from switching and generating noise) 5:4 oversampling 00: normal operation (1x sampling) 01:2x oversampling, 2 samples averaged at adc output 10:4x oversampling, 4 samples averaged at adc output 11:8x oversampling, 8 samples averaged at adc output in oversampling mode, the htotal, dc restore/ablc start, dc restore width, and ablc width values are automatically multiplied by the oversampling ra tio. the pixel clock is divided by the oversampling ratio when the data is decimated. decimator is reset on trailing edge of hsync. 6 rgb2yuv color space conversion enable 0: csc disabled 1: csc enabled note: the data delay through the entire afe is identical with csc on and csc off. register listing (continued) address register (default value) bits function name description ISL51002
16 fn6164.2 september 19, 2007 0x29 output format 2, (0x00) 0 dataclk polarity 0: pixel data changes on falling edge (default) 1: pixel data changes on rising edge 1 field output polarity 0: odd = low, even = high (default) 1: odd = high, even = low 2 macrovision 0: digitize macr ovision encoded signals (default) 1: blank afe output for macrovision encoded signals. if macrovision is detected, afe output is always 0x00 0x00 0x00 for rgb, or 0x00, 0x80, 0x80 for yuv. 3hs out polarity 0: active high (default) 1: active low 4hs out lock edge 0: hs out ?s leading edge is locked to selected hsync in ?s lockedge. trailing edge moves forward in time as hsout width is increased (default). 1: hs out ?s trailing edge is locked to selected hsync in ?s lockedge. leading edge moves backward in time as hs out width is increased. 5 xtalclkout frequency 0: xtalclkout= f crystal (default) 1: xtalclkout= f crystal /2 6 enable xtalclkout 0 = xtalclkout is logic low (default) 1 = xtalclkout enabled 0x2a hs out width, (0x10) 7:0 hs out width hs out width in pixels, 0x00 to 0xff. hs out lock edge determines whether leading or trailing edge is locked to hsync in 0x2b output signal disable, (0xff) note: all digital outputs are tristated by default to ease multiplexing with other afes 0 tri-state red 0 = outputs enabled 1 = outputs in tri-state 1 tri-state green 0 = outputs enabled 1 = outputs in tri-state 2 tri-state blue 0 = outputs enabled 1 = outputs in tri-state 3 tri-state sync 0 = hs out , hsync out , vsync out enabled 1 = outputs in tri-state 4 tri-state dataclk 0 = output enabled 1 = output in tri-state 5 tri-state dataclkb 0 = output enabled 1 = output in tri-state 6 tri-state de 0 = output enabled 1 = output in tri-state 7 tri-state field 0 = output enabled 1 = output in tri-state 0x2c power control, (0x00) 0 red power down 0 = red adc operational (default) 1 = red adc powered down 1 green power down 0 = green adc operational (default) 1 = green adc powered down 2 blue power down 0 = blue adc operational (default) 1 = blue adc powered down 3 pll power down 0 = pll operational (default) 1 = pll powered down register listing (continued) address register (default value) bits function name description ISL51002
17 fn6164.2 september 19, 2007 0x2d xtal clock freq, (0x19) 4:0 crystal clock frequency crystal clock frequency in mhz (decimal). 0x00: test mode, do not use. 0x01 through 0x0a: 10mhz, apll div = 35 (0x23) 0x0b: 11mhz, apll div = 32 0x0c: 12mhz, apll div = 30 0x0d: 13mhz, apll div = 27 0x0e: 14mhz, apll div = 25 0x0f: 15mhz, apll div = 24 0x10: 16mhz, apll div = 22 0x11: 17mhz, apll div = 21 0x12: 18mhz, apll div = 20 0x13: 19mhz, apll div = 19 0x14: 20mhz, apll div = 18 0x15: 21mhz, apll div = 17 0x16: 22mhz, apll div = 16 0x17: 23mhz, apll div = 16 0x18: 24mhz, apll div = 15 0x19: 25mhz, apll div = 14 0x1a: 26mhz, apll div = 14 0x1b: 27mhz, apll div = 13 0x1c: 28mhz, apll div = 13 0x1d: 29mhz, apll div = 13 0x1e: 30mhz, apll div = 12 0x1f: 31mhz, apll div = 12 0x2e afe bandwidth, (0x0e) 3:0 afe bw -3db point for afe lowpass filter 0: 9mhz 1: 10mhz 2: 11mhz 3: 12mhz 4: 14mhz 5: 17mhz 6: 21 mhz 7: 24mhz 8: 30mhz 9: 38mhz a: 50mhz b: 75mhz c: 83mhz d: 105mhz e: 149mhz (default) f: 450mhz 0x2f hsync slicer thresholds, (0x44) all values referred to voltage at hsync input pin, 300mv hysteresis 3:0 selected hsync threshold hsync slicer thre shold for selected input channel (only 3-bits used, lowest bit is ignored): 0000 = lowest (0.4v) 0100 = default (1.15v) 1111 = highest (3.2v) 7:4 unselected hsync threshold hsync threshold for monitori ng unselected inputs. see selected hsync threshold for values. 0x30 sog slicer thresholds, (0x66) 3:0 sog threshold sog slicer threshold: 0000 = lowest (0mv) 0110 = default (120mv) 1111 = highest (300mv) register listing (continued) address register (default value) bits function name description ISL51002
18 fn6164.2 september 19, 2007 0x31 hsync/sog config, (0x04) 3:0 glitch filter width 0: 16 crystal clocks 1: 17 crystal clocks 2: 1 crystal clocks 3: 2 crystal clocks 4: 3 crystal clocks (default) 5: 4 crystal clocks 6: 5 crystal clocks 7: 6 crystal clocks 8: 7 crystal clocks 9: 8 crystal clocks 10: 9 crystal clocks 11: 10 crystal clocks 12: 11crystal clocks 13: 12 crystal clocks 14: 13 crystal clocks 15: 14 crystal clocks 4 sync glitch filter disable 0: glitch filter enabled 1: glitch filter disabled 5 sog hyst disable 0: 40mv hysteresis enabled 1: 40mv hysteresis disabled 6 sog lpf disable 0: 14mhz so g low pass filter enabled 1: 14mhz sog low pass filter disabled 0x32 sync polling control, (0x00) 0 ch0 polling 0: enable 1: disable 1 ch1 polling 0: enable 1: disable 2 ch2 polling 0: enable 1: disable 3 ch3 polling 0: enable 1: disable 4 ch0 connector type 0: rgb db15 (poll for hsync, csync, and sog) 1: component (poll for sog only) 5 ch1 connector type 0: rgb db15 (poll for hsync, csync, and sog) 1: component (poll for sog only) 6 ch2 connector type 0: rgb db15 (poll for hsync, csync, and sog) 1: component (poll for sog only) 7 ch3 connector type 0: rgb db15 (poll for hsync, csync, and sog) 1: component (poll for sog only) measurement registers 0x40 hsync period msb, (read only) 7:0 hsync period msb these registers report a 16-bit value containing the number of crystal clocks inside a 16 consecutive hsync period window. this means the 16-bit number will reflect one hsync period with 1/16 lsb resolution - the last 4-bits of the measurement will be fractional. 0x41 hsync period lsb, (read only) 7:0 hsync period lsb 0x42 hsync width msb, (read only) 7:0 hsync width msb these registers report a 16-bit value containing the number of crystal clocks inside 16 cons ecutive hsync pulses. this means the 16-bit number will reflect one hsync pulse width with 1/16 lsb resolution - the last 4-bits of the measurement will be fractional. 0x43 hsync width lsb, (read only) 7:0 hsync width lsb register listing (continued) address register (default value) bits function name description ISL51002
19 fn6164.2 september 19, 2007 0x44 vsync period msb, (read only) 3:0 vsync period msb these bits report a 12-bit value containing the width of one frame (= 2 fields for interlaced, = 1 field for progressive) of video. vsync period for measured channel = 256*vsync period msb + vsync period lsb units are either number of hsync periods or number of fcrystal/512 periods, depending on setting of vsync units register. 0x45 vsync period lsb, (read only) 7:0 vsync period lsb 0x46 vsync width, (read only) 6:0 vsync width this register reports a 7-bit value containing the width the vsync pulse. the value returned is for true vsync only: it does not include serrations, eq pulses, macrovision pulses, etc. units are either number of hsync periods or number of fcrystal/512 periods, depending on setting of vsync units register. 0x47 de start msb, (0x00) 1:0 de start msb 10-bit val ue containing the number of pixel clocks between the trailing edge of hs out and the first valid pixel. sxga default values. 0x48 de start lsb, (0xf6) 7:0 de start lsb 0x49 de width msb, (0x05) 3:0 de width msb 12-bit valu e containing the number of visible image pixels. sxga default values. 0x4a de width lsb, (0x00) 7:0 de width lsb 0x4b line start msb, (0x00) 1:0 line start msb 10-bit val ue containing the number of lines between the trailing edge of vsync out and the first valid line. sxga default values. 0x4c line start lsb, (0x26) 7:0 line start lsb 0x4d line width msb, (0x04) 3:0 line width msb 12-bi t value containing the num ber of visible lines. sxga default values. 0x4e line width lsb, (0x00) 7:0 line width lsb 0x4f measurement configuration, (0x00) 0 vsync units 0: vsync measurement reported in units of lines (hsync periods) 1: vsync measurement reported in units of 512 crystal clock periods 1 vsync_linecount_mode 0: new method (integer count of hs out s) 1: old method (time measurement with rounding errors) auto adjust registers 0x50 phase adj cmd fn, (0x00) 2:0 padj function note: a wr ite to this register executes the command contained in the three lsbs of the word written. commands: 000: reserved 001: reserved 010: reserved 011: setphase 100: set de 101: reserved 110: reserved 111: reserved 0x51 phase adj status, (read only) 7 padj busy 0: phase adjustment function idle 1: phase adjustment in progress register listing (continued) address register (default value) bits function name description ISL51002
20 fn6164.2 september 19, 2007 0x52 phase adj mask v, (0x01) 2:0 padj exclude v2 vertical line mask: how many lines to exclude before the leading edge of vsync 000: 0 lines 001: 1 lines (default) 010: 2 lines 011: 4 lines 100: 6 lines 101: 8 lines 110: 10 lines 111: 12 lines 3n/a 6:4 padj e xclude v1 choose how many lines to exclude after the leading edge of vsync (typically used to exclude vbi data) 000: 5 lines (default) 001: 18 lines 010: 19 lines (480i) 011: 20 lines (1080i) 100: 22 lines (576i) 101: 25 lines (720p) 110: 41 lines (480p/1080p) 111: 44 lines (576p) 0x53 horizontal pixel mask 1, (0x01) 7:0 padj exclude h1 if a value of ?n? is prog rammed in this register, 2*n pixels after the active edge of hs out will be excluded from data collection. must be >0 for proper operation. 0x54 horizontal pixel mask 2, (0x01) 7:0 padj exclude h2 if a value of ?n? is programmed in this register, 2*n pixels before the active edge of hs out will be excluded from data collection. must be >0 for proper operation. 0x55 phase adjust command options, (0x20) 0 padj blue disable enable/disabl e blue color for measurement 0: enable 1: disable 1 padj green disable enable/disable green color for measurement 0: enable 1: disable 2 padj red disable enable/disabl e red color for measurement 0: enable 1: disable 3 padj adjust search option search option for auto phase adjustment 0: best phase 1: worst phase 4 padj adjust speed this is a hidden bit for customers. it decides whether the search steps are 28 (fast) or 64 vsync intervals (slow). 0: 28 vsyncs 1: 64 vsyncs 5 update phase on vsync 0: phase updated immediately 1: phase updated on vsync (default) 6 padj soft reset 0: normal operation 1: reset all phase adjust state machines take high then low to reset phase adjust block 7 reserved set to 0 register listing (continued) address register (default value) bits function name description ISL51002
21 fn6164.2 september 19, 2007 0x56 transition threshold, (0x0a) 7:0 padj threshold threshold of transitions visible for capturing. these are the 8 msbs of the 10-bit threshold word used for phase quality measurements. the actual 10- bit threshold used equals the value in this register times 4. 0x57 phase adjust data 3, (read only) 7:0 reserved reserved 0x58 phase adjust data 2, (read only) 7:0 reserved reserved 0x59 phase adjust data 1, (read only) 7:0 reserved reserved 0x5a phase adjust data 0, (read only) 7:0 reserved reserved 0x60 afe ctrl, (0x00) 0 reserved set to 0 1 700mv calibration 0: normal operation 1: all three inputs connected to internal ~700mv reference voltage 2 coast clamp enable 0: dc restore clamping and ablc suspended during coast and macrovision (default) 1: dc restore clamping and ablc continue during coast 3 reserved set to 0 4 blue midscale 0: half scale analog shift not added to blue channel (uv) 1: half scale analog shift added to blue channel (yrgb) 5 green midscale 0: half scale analog shift not added to green channel (uv) 1: half scale analog shift added to green channel (yrgb) 6 red midscale 0: half scale analog shift not added to red channel (uv) 1: half scale analog shift added to red channel (yrgb) 7 midscale override 0: midscale determined by rgb/yuv bit in user control section ? settings in 0x60[6:4] are ignored (default). 1: midscale determined by 0x60[6:4] 0x61 adc ctrl, (0x00) 0 dither enable 0: dither disabled (default) 1: dither enabled 1 dither amplitude 0: 16 lsbs (default) 1: 8 lsbs 3:2 dither increment 00: every pixel (default) 01: every hsync 10 and 11: every vsync 4 dither seed reset set to 1 and then to 0 to reset register listing (continued) address register (default value) bits function name description ISL51002
22 fn6164.2 september 19, 2007 technical highlights the ISL51002 provides all the features of traditional triple channel video afes, but adds several next-generation enhancements, bringing performance and ease of use to new levels. dpll all video afes must phase lock to an hsync signal, supplied either directly or embedded in the video stream (sync on green). historically this has been implemented as a traditional analog pll. at sxga and lower resolutions, an analog pll solution has proven adequate, if somewhat troublesome (due to the need to adjust charge pump currents, vco ranges and other parameters to find the optimum trade-off for a wide range of pixel rates). as display resolutions and refresh rates have increased, however, the pixel period has shrunk. an xga pixel at a 60hz refresh rate has 15.4ns to change and settle to its new value. but at uxga 75hz, the pixel period is 4.9ns. most consumer graphics cards (even the ones with ?350mhz? dacs) spend most of that time slewing to the new pixel value. the pixel may settle to its final value with 1ns or less before it begins slewing to the next pixel. in many cases it rings and never settles at all. so precision, low-jitter sampling is a fundamental requ irement at these speeds, and a difficult one for an analog pll to meet. the ISL51002's dpll has less than 250ps of jitter, peak to peak, and independent of the pixel rate. the dpll generates 64 phase steps per pixel (vs. the industry standard 32), for fine, accurate positioning of the sampling point. the crystal- locked nco inside the dpll comple tely eliminates drift due to charge pump leakage, so there is inherently no frequency or phase change across a line. an intelligent all-digital loop filter/controller eliminates the need for the user to have to program or change anything (exc ept for the number of pixels) to lock over a range from inte rlaced video (10mhz or higher) to uxga 60hz (165mhz, with the ISL51002-165). the dpll eliminates much of the performance limitations and complexity associated with noise-free digitization of high speed signals. automatic black level compensation (ablc?) and gain control traditional video afes have an offset dac prior to the adc, to both correct for offsets on the incoming video signals and add/subtract an offset for user ?brightness control? without sacrificing the 10-bit dynamic range of the adc. this solution is adequate, but it places significant requirements on the system's firmware, which must execute a loop that detects the black portion of the signal and then servos the offset dacs until that offset is nulled (or produces the desired adc output code). once this has been accomplished, the offset (both the offset in the afe and the offset of the video card generating the signal) is subject to drift, the temperature inside a monitor or projector can easily change +50c between power-on/of fset calibration on a cold morning and the temperature reached once the monitor and the monitor's environment have reached steady state. offset can drift significantly over +50c, reducing image quality and requiring that the user do a manual calibration once the monitor has warmed up. in addition to drift, many afes exhibit interaction between the offset and gain controls. when the gain is changed, the magnitude of the offset is changed as well. this again increases the complexity of the firmware as it tries to optimize gain and offset settings for a given video input signal. instead of adjusting just the offset, then the gain, both have to be adjusted interactively until the desired adc output is reached. the ISL51002 simplifies offset and gain adjustment and completely eliminates offset drift using its automatic black level compensation (ablc?) function. ablc? monitors the black level and continuously adjusts the ISL51002's 10-bit offset dacs to null out the offset. any offset, whether due to the video source or the ISL51002's analog amplifiers, is eliminated with 10-bit accuracy. any drift is compensated for well before it can have a visible effect. manual offset adjustment control is still availabl e (a 10-bit register allows the firmware to adjust the offset 64 codes in exactly 1adc lsb increments). gain is now completely independent of offset (adjusting the gain no longer affects the offset, so there is no longer a need to program the firm ware to cope with interactive offset and gain controls). finally, there should be no concerns over ablc? itself introducing visible artifacts; it doesn't. ablc? functions at a very low frequency, changing the offset in 1 lsb increments, so it can't cause visible brightness fluctuations. and once ablc? is locked, if the offset doesn't drift, the dacs won't change. if desired, ablc? c an be disabled, allowing the firmware to work in the traditional way, with 10-bit offset dacs under the firmware's control. gain and offset control to simplify image optimization algorithms, the ISL51002 features fully-independent ga in and offset adjustment. changing the gain does not affect the dc offset, and the weight of an offset dac lsb does not vary depending on the gain setting. the full-scale gain is set in th e three sets of registers (0x12 and 0x13 - 0x16 and 0x17). each set of gain registers is divided into an 8-bit msb register (0x12, 0x14 and 0x16) and a 2-bit lsb register providing a 10-bit gain value that both allows for 8-bit control compatible with the 8-bit family of afes and allows for the expansion of the gain resolution in future afes without significant firmware changes. the ISL51002 can accept input signals with amplitudes ranging from 0.35v p-p to 1.4v p-p . ISL51002
23 fn6164.2 september 19, 2007 the offset controls shift the entire rgb input range, changing the input image brightness. thr ee separate registers provide independent control of the r, g, and b channels. their nominal setting is 0x8000, whic h forces the adc to output code 0x0000 (or 0x200 for the r (pr) and b (pb) channels in ypbpr mode) during the back porch period when ablc? is enabled. functional description inputs the ISL51002 digitizes analog video inputs in both rgb and component (ypbpr) formats, with or without embedded sync (sog). rgb inputs for rgb inputs, the black/blank levels are identical and equal to 0v. the range for each color is typically 0v to 0.7v from black to white. hsync and vsync are separate signals. component ypbpr inputs in addition to rgb and rgb with sog, the ISL51002 has an option that is compatible with the component ypbpr video inputs typically generated by dvd players. while the ISL51002 digitizes signals in these color spaces, it can only perform color space conversion from rgb to yuv; if it digitizes an rgb signal, it outputs digital rgb or yuv, while if it digitizes a ypbpr signal, it outputs digital ycbcr, also called yuv. the luminance (y) signal is applied to the green channel and is processed in a manner identical to the green input with sog described previously. the color difference signals pb and pr are bipolar and swing both above and below the black level. when the ypbpr mode is enabled, the black level output for the color difference channels shifts to a mid scale value of 0x200. sett ing configuration register 0x10[4] = 1 enables the ypbpr signal processing mode of operation. the ISL51002 can optionally decimate the incoming data to provide a 4:2:2 output str eam (configuration register 0x28[0] = 1) as shown in table 2. rgb to yuv color space converter (csc) for rgb inputs, the internal color space converter, when enabled (register 0x28-bit [6] = 1), will convert from the rgb color space to the yuv (ycbcr) color space using the following conversion formulas: y = 0.299r + 0.587g + 0.114b u = -0.172r - 0.339g + 0.511b + 512 v = 0.511r - 0.428g - 0.083b + 512 input coupling inputs can be either ac-coupled (default) or dc-coupled (see register 0x10[3]). ac coupling is usually preferred since it allows video signals with substantial dc offsets to be accurately digitized. the ISL51002 provides a complete internal dc-restore function, including the dc restore clamp (see figure 1) and programmable clamp timing (registers 0x24, 0x25, and 0x26). when ac-coupled, the dc restore clamp is applied every line, a programmable number of pixels after the trailing edge of hsync. if register 0x60[2] = 0 (the default), the clamp will not be applied while the dpll is coasting, preventing any clamp voltage errors from composite sync edges, equalization pulses, or macrovision signals. after the trailing edge of hsync, the dc restore clamp is turned on after the number of pixels specified in the dc restore and ablc? starting pixel registers (0x24 and 0x25) has been reached. the clamp is applied for the number of pixels specified by the dc restore clamp width register (0x26). the clamp can be applied to the back porch of the video, or to the front porch (by increasing the dc restore and ablc? starting pixel registers so all the active video pixels are skipped). note: the trilevel detect for sync on green (sog) utilizes the digitized data from the selected green video channel. if trilevel sync is present, the default dc clamp start position will clamp at the top of the tril evel sync pulse giving a false negative for trilevel detect and clamping off the bottom half of the green video. if you have an indication of active sog you must move the clamp start to a value greater than 0x30 to check to see if the tri-level sync is present. if dc-coupled operation is desir ed, the input to the adc will be the difference between the input signal (r in 1, for example) and that channel?s ground reference (rgb gnd 1 in that example). table 1. yuv mapping (4:4:4) input signal ISL51002 input channel ISL51002 output assignment output signal y green green y 0 y 1 y 2 y 3 pb blue blue u 0 u 1 u 2 u 3 pr red red v 0 v 1 v 2 v 3 table 2. yuv mapping (4:2:2) input signal ISL51002 input channel ISL51002 output assignment output signal y green green y 0 y 1 y 2 y 3 pb blue blue driven low pr red red u 0 v 0 u 2 v 2 ISL51002
24 fn6164.2 september 19, 2007 sog for component ypbpr signals, the sync signal is embedded on the y-channel?s video, which is connected to the green input, hence the name sog (sync on green). the horizontal sync information is encoded onto the video input by adding the sync tip during the blanking interval. the sync tip level is typically 0.3v below the video black level. to minimize the loading on the green channel, the sog input for each of the green channels should be ac-coupled to the ISL51002 through a series combination of a 10nf capacitor and a 500 resistor. sog slicer (figure 2) the sog input has programmable threshold, 40mv of hysteresis, and an optional low pass filter than can be used to remove high frequency video spikes (generated by overzealous video peaking in a dvd player, for example) that can cause false sog triggers. the sog threshold sets the comparator threshold relative to the sync tip (the bottom of the sog pulse). inside the ISL51002, a 1a pulldown ensures that each sync tip triggersthe clamp circuit causing the tip to be clamped to a 600mv level. a comparator compares the sog signal with an internal 4-bit programmable threshold level reference ranging from 0mv to 300mv above the sy nc clamp level. the sog threshold level, hysteresis, and low-pass filter is programmed via registers 0x30and 0x31. if the sync-on-green function is not needed, the sog in pin(s) may be left unconnected. sync processing the ISL51002 can process sync signals from 3 different sources: discrete hsync and vsync, composite sync on the hsync input, or composite sync from a sync-on-green (sog) signal embedded on the green video input. the ISL51002 has sync activity dete ct functions to help the firmware determine which sync source is available. macrovision the ISL51002 automatically detects the presense of macrovision-encoded video. when macrovision is detected, it generates a mask signal that is anded with the incoming sog csync signal to remove the macrovision before the hsync goes to the pll. no additional programming is required to support macrovision. the mask signal is also applied to the hsync out signal. when sync mask disable = 0, any macrovision present on the incoming sync will not be visible on hsync out . if the application requires the macrovision pulses to be visible on hsync out , set the hsync out mask disable bit (register 0x7a-bit 4). headswitching from an alog videotape signals occasionally this afe may be used to digitize signals coming from analog videotape sources. the most common example of this is a digital vcr (which for best signal quality would be connected to this afe with a component ypbpr connection). if the digital vcr is playing an older analog vhs tape, the sync signals from the vcr may contain the worst of the traditional analog tape artifacts: headswitching. headswitching is traditionally th e enemy of plls with large capture ranges, because a headswitch can cause the hsync period to change by as much as 90%. to the pll, this can look like a frequency change of -50% to +900%, causing errors in the output frequency (and obviously the phase) to change. subsequen t hsyncs have the correct, original period, but most analog plls will take dozens of lines to settle back to the correct frequency and phase after a headswitch disturbance. this causes the top of the image to ?tear? during normal playback. in ?trick modes? (fast forward and rewind), the hsync signal has multiple headswitch-like discontinuities, and many plls never settle to the correct value before the next headswitch, rendering the image completely unintelligible. figure 1. video flow (including ablc?) r(gb) in 0 clamp generation r(gb) gnd 0 r(gb) in 1 r(gb) gnd 1 vga0 vga1 vga2 vga3 v in + v in - dc restore clamp dac v clamp 10-bit adc offset dac fixed offset ablc? ablc? offset control registers ablc? fixed offset 0x000 to ablc block to output formatter 10 10 10 10 10 10 10 automatic black level compensation (ablc?) loop dc restoration input bandwidth pga bandwidth control 10 r(gb) in 2 r(gb) gnd 2 r(gb) in 3 r(gb) gnd 3 ISL51002
25 fn6164.2 september 19, 2007 intersil?s dpll has the capability to correct large phase changes almost instantly by maximizing the phase error gain while keeping the frequency gain relatively low. this is done by changing the contents of register 0x74 to 0x4c. this increases the phase error gain to 100%. because a phase setting this high will slightly in crease jitter, the default setting (0x49) for register 0x74 is recommended for all other sync sources. sync timing measurement the ISL51002 analyzes the timing characteristics of the sysnc signals for the currently selected input channel and presents the results in registers 0x40 through 0x0x46. the hsync period and pulse width values are 16-bit numbers representing the number of crystal clocks in 16 consecutive periods or pulse widths giving a measurment resolution of 1/16th of a crystal clock. the vsync period is a 12-bit number representing the number of either hsyncs or uni ts of 512 crystal clocks that occure in one video frame. the default is to count hsync pulses but setting register 0x4f[0] = 1 changes to the units to crystal clock 512. the vsync pulse width is a 12 -bit number representing the number of either hsyncs or uni ts of 512 crystal clocks that occure in one vsync. the default is to count hsync pulses but setting register 0x4f[0] = 1 changes to the units to crystal clock 512. pga the ISL51002?s programmable gain amplifier (pga) has a nominal gain range from 0.5v/v (-6db) to 2.0v/v (+6db). the transfer function is: where gaincode is the value in the gain register for that particular color. note that fo r a gain of 1v/v, the gaincode should be 85 (0x55). this is a different center value than the 128 (0x80) value used by some other afes, so the firmware should take this into account when adjusting gains. the pgas are updated by the internal clamp signal once per line. in normal operation this means that there is a maximum delay of one hsync period between a write to a gain register for a particular color and the corresponding change in that channel?s actual pga gain. if there is no regular hsync/sog source, or if the external clamp option is enabled (register 0x10[7:6]) but there is no external clamp signal being generated, it may take up to 100ms for a write to the gain register to update the pga. this is not an issue in normal operation with rgb and ypbpr signals. offset dac the ISL51002 features a 10-bit digital-to-analog converter (dac) to provide extremely fine control over the full channel offset. the dac is placed after the pga to eliminate interaction between the pga (controlling ?contrast?) and the offset dac (controlling ?brightness?). in normal operation, the offset dac is controlled by the ablc? circuit, ensuring that the offset is always reduced to sub-lsb levels (see the following ablc? section for more information). when ablc? is enabled, the offset register pairs (0x18 and 0x 19 through 0x1c and 0x1d) control a digital offset added to or subtracted from the output of the adc. this mode provides the best image quality and eliminates the need for any offset calibration. if desired, ablc? can be disabled (0x27[0] = 1) and the offset dac programmed manually, with the 8 most significant bits in register s 0x18, 0x1a,10x1c, and the 2 least significant bits in regi sters 0x19[7:6], 0x1b[7:6] and 0x1d[7:6]. - + green slicer dac 600mv to 900mv + ? 600mv sog in 1 a 4 r in c in 10nf 500 clamp slice filter on/off hist on/off - + syncout figure 2. sog slicer gain v v --- - ?? ?? 0.5 gaincode 170 ----------------------------- + = (eq. 1) ISL51002
26 fn6164.2 september 19, 2007 the default offset dac range is 127 adc lsbs. setting 0x27[1] = 1 reduces the swing of the offset dac by 50%, making 1 offset dac lsb the weight of 1/2 of an adc lsb. this provides the finest offset control and applies to both ablc? and manual modes. automatic black level compensation (ablc?) ablc is a function that continuously removes all offset errors from the incoming video signal by monitoring the offset at the output of the adc and servoing the 10-bit analog dac to force those errors to zero. when ablc is enabled, the user offset control is a digital adder, with 10-bit resolution. when the ablc function is enabled (0x27[0] = 0), the ablc function is executed every li ne after the trailing edge of hsync. if register 0x60[2] = 0 (the default), the ablc function will be not be triggered while the dpll is coasting, preventing any composite sync edges, equalization pulses, or macrovision signals from corrupting the black data and potentially adding a small error in the ablc accumulator. after the trailing edge of hsync, the start of ablc is delayed by the number of pixels specified in registers 0x24 and 0x25. after that delay, the number of pixels specified by register 0x27[3:2] are averaged together and added to the ablc?s accumulator. the accumulator stores the average black levels for the number of lines specified by register 0x27[6:4], which is then used to generate a 10-bit dac value. the ablc can be set to allow the capture of signals below black by setting registers 0x 65, 0x66 and 0x67 to a number that will controll the target for the ablc servo loop. if you set register 0x65 to 0x04 then the ab lc will adjust the offset dac to produce an average output code on the red channel of 0x10 during the back porch. effectivly, the black level for a given channel will be set to the value of its ablc offset target register times four. (output = register 0x65, 0x66 or 0x67 times 4). adc the ISL51002 features 3 fully differential, high-speed 10-bit adcs. clock generation a digital phase lock loop (dpll) is employed to generate the pixel clock frequency. the hsync input and the external xtal provide a reference frequency to the pll. the pll then generates the pixel clock frequency that equal to the incoming hsync frequency times the htotal value programmed into registers 0x1e and 0x1f. the stability of the clock is very important and correlates directly with the quality of the image. during each pixel time transition, there is a small window where the signal is slewing from the old pixel amplitude and settling to the new pixel value. at higher frequencies, the pixel time transitions at a faster rate, which makes the stable pixel time even smaller. any jitter in the pixel clock reduces the effective stable pixel time and thus the sample window in which pixel sampling can be made accurately. sampling phase the ISL51002 provides 64 low-jitter phase choices per pixel period, allowing the firmware to precisely select the optimum sampling point. the sampling phase register is 0x20. auto phase adjust the ISL51002 provides the ability to automatically adjust the sampling phase to the best setting. set register 0x50 to 0x03 to activate the auto phase adjust function. data enable (de) generator the ISL51002 provides a signal that is high during the active video time when properly configured. this signal is used by devices such as dvi/hdmi transmitters to gate the active portion of the video and ignore the h and v sync times. auto de adjust the ISL51002 provides the ability to automatically adjust the de to the settings that are very close to ideal. the determination of exactly where on a line the active video starts and ends depends heavily on the video content being analyzed making the de settings difficult to automate. the customer will be required to fine tune the de settings after the auto adjust routine has comp leted. set register 0x50 to 0x04 to activate the auto de adjust function hsync slicer to further minimize jitter, the hsync inputs are treated as analog signals, and brought into a precision slicer block with thresholds programmable in 400mv steps with 240mv of hysteresis, and a subsequent digita l glitch filter that ignores any hsync transitions within 100ns of the initial transition. this processing greatly incr eases the afe?s rejection of ringing and reflections on the hsync line and allows the afe to perform well even with pathological hsync signals. voltages given above and in the hsync slicer register description are with respect to a 3.3v sync signal at the hsync in input pin. to achieve 5v compatibility, a 680 series resistor should be placed between the hsync source and the hsync in input pin. relative to a 5v input, the hysteresis will be 240mv*5v/3.3 v = 360mv, and the slicer step size will be 400mv*5v/3.3v = 600mv per step. sync status and polarity detection the ch0 and ch1 activity status register (0x02) and the ch2 and ch3 activity status register (0x03) continuously monitor all 12syn c inputs (vsync in , hsync in , and sog in for each of 4 channels) and report their status, while the selected input channel characte ristics register (0x01) gives more detailed information on the curently selected input channel. however, accurate sync acti vity detection is always a challenge. noise and repetitive video patterns on the green ISL51002
27 fn6164.2 september 19, 2007 channel may look like sog activity when there actually is no sog signal, while non-standard sog signals and trilevel sync signals may have amplitude s below the default sog slicer levels and not be easily detected. as a consequence, not all of the activity detect bits in the ISL51002 are correct under all conditions. for best sog operation, the sog low pass filter (register 0x04[4] should always be enabled to reject the high frequency peaking often seen on video signals. hsync and vsync activity detect activity on these bits always indicates valid sync pulses, so they should have the highest priority and be used even if the sog activity bit is also set. sog activity detect the sog activity detect bit moni tors the output of the sog slicer, looking for 64 consecutive pulses with the same period and duty cycle. if there is no signal on the green (or y) channel, the sog slicer will clamp the video to a dc level and will reject any sporadic noise. there should be no false positive sog detects if there is no video on green (or y) channel. if there is video on green (or y) channel with no valid sog signal, the sog activity dete ct bit may sometimes report false positives (it will detect sog when no sog is actually present). this is due to t he presence of video with a repetitive pattern that create s a waveform si milar to sog. for example, the desktop of a pc operating system is black during the front porch, horizonta l sync, and back porch, then increases to a larger value for the video portion of the screen. this creates a repetitive video waveform very similar to sog that may falsely trigger the sog activity detect bit. however, in these cases where there is active video without sog, the sync information will be provided either as separate h and v sync on hsync in and vsync in , or composite sync on hsync in . hsync in and vsync in should therefore be used to q ualify sog. the sog active bit should only be considered valid if hsync activity detect = 0. note: some patter n generators can output hsync and sog simultaneously, in which case both the hsync and the sog activity bits will be set, and valid. even in this case, howe ver, the monitor sh ould still choose hsync over sog. trilevel sync detect the trilevel detect for sync on green (sog) utilizes the digitized data from the selected green video channel. if trilevel sync is present, the default dc clamp start position will clamp at the top of the trilevel sync pulse giving a false negative for trilevel detect and clamping off the bottom half of the green video. if you have an indication of active sog you must move the clamp start to a value greater than 0x30 to check to see if the trilevel sync is present. sync output signals the ISL51002 has a pair of hsync output signals, hsync out and vsync out , and hs out . hsync out and vsync out are buffered versions of the incoming sync signals; no synchronization is done. these signals are used for mode detection hs out is generated by the ISL51002?s logic and is synchronized to the output dataclk and the digital pixel data on the output databus. hs out is used to signal the start of a new line of digital data. both hsync out and vsync out (including the sync separator function) remain acti ve in power-down mode. this allows them to be used in c onjunction with the sync status registers to detect valid video without powering up the ISL51002. hsync out hsync out is an unmodified, buffered version of the incoming hsync in or sog in signal of the selected channel, with the incoming signal?s period, polarity, and width to aid in mode detection. hsync out will be the same format as the incoming sync signal: either horizontal or composite sync. if a sog input is selected, hsync out will output the entire sog signal, including the vsync portion, pr e-/post-equalization pulses if present, and macrovision pulses if present. hsync out remains active when the ISL51002 is in power-down mode. hsync out is generally used for mode detection. vsync out vsync out is an unmodified, buffere d version of the incoming vsync in signal of the selected channel, with the original vsync period, polarity, and width to aid in mode detection. if a sog input is selected, this si gnal will output the vsync signal extracted by the ISL51002?s sync slicer. extracted vsync will be the width of the embedded vsync pulse plus pre- and post- equalization pulses (if present). macrovision pulses from an ntsc dvd source will lengthen the width of the vsync pulse. macrovision pulses from other sources (pal dvd or videotape) may appear as a second vsync pulse encompassing the width of the macrovision. see th e macrovision section for more information. vsync out (including the sync separator function) remains active in power-down mode. vsync out is generally used for mode detection, start of field detection, and even/odd field detection. hs out hs out is generated by the ISL51002?s control logic and is synchronized to the output dataclk and the digital pixel data on the output databus. its trailing edge is aligned with pixel 0. its width, in units of pixels, is determined by register 0x2a, and its polarity is determined by regi ster 0x29[3]. as the width is increased, the trailing edge stays aligned with pixel 0, while the leading edge is moved backwards in time relative to pixel 0. hs out is used by the scaler to signal the start of a new line of pixels. ISL51002
28 fn6164.2 september 19, 2007 crystal oscillator an external 12mhz to 27mhz crystal supplies the low-jitter reference clock to the dpll. the absolute frequency of this crystal within this range is unimp ortant, as is the crystal?s temperature coefficient, allowing use of less expensive, lower-grade crystals. as an alternative to a crystal, the xtal in pin can be driven with a 3.3v cmos-level external clock source at any frequency between 12mhz and 27mhz. the ISL51002?s jitter specification assumes a lo w-jitter crystal source. if the external clock source has incr eased jitter, the sample clock generated by the dpll may exhibi t increased jitter as well. emi considerations there are two possible sources of emi on the ISL51002: crystal oscillator the emi from the crystal oscillator is negligible. this is due to an amplitude-regulated, low voltage sine wave oscillator circuit, instead of the typical high-gain square wave inverter-type oscillator, so there are no harmonics. the crystal oscillator is not a significant source of emi. digital output switching this is the largest potential source of emi. however, the emi is determined by the pcb layout and the loading on the databus. the way to control this is to put series resistors on the output of all the digital pins (as our demo board and reference circuits show). these resistors should be as large as possible, while still meeting the setup and hold timing requirements of the scaler. we recommend starting with 22 . if the databus is heavily loaded (long traces, many other part on the same bus), this value may need to be reduced. if the databus is lightly loaded, it may be increased. intersil?s recommendations to minimize emi are: ? minimize the databus trace length ? minimize the databus capacitive loading. if emi is a problem in the final design, increase the value of the digital output series resistors to reduce slew rates on the bus. this can only be done as long as the scaler?s setup and hold timing requirements continue to be met. standby mode the ISL51002 can be placed into a low power standby mode by writing a 0x0f to register 0x2c, powering down the triple adcs, the dpll, and most of the internal clocks. to allow input monitoring and mode detection during power- down, the following blocks remain active: ? serial interface (including the crystal oscillator) to enable register read/write activity ? activity and polarity detect functions (registers 0x01 and 0x02) ? the hsync out and vsync out pins (for mode detection) initialization the ISL51002 initializes with def ault register settings for an ac-coupled, rgb input on the vga1 channel, with a 30-bit output. reset the ISL51002 has a power on reset (por) function that resets the chip to its default state when power is initially applied, including resetting all the registers to their default settings as described in the register listing. the por function takes 512k crystal clocks (~21ms at 25mhz) to complete. the external reset pin duplicates the reset function of the por without having to cycle the power supplies. the reset pin does not need to be used in normal operation and can be tied high. ISL51002 serial communication overview the ISL51002 uses a 2-wire serial bus for communication with its host. scl is the serial clock line, driven by the host, and sda is the serial data line, which can be driven by all devices on the bus. sda is open drain to allow multiple devices to share the same bus simultaneously. communication is accomplished in three steps: 1. the host selects the ISL51002 it wishes to communicate with. 2. the host writes the initial ISL51002 configuration register address it wishes to write to or read from. 3. the host writes to or reads from the ISL51002?s configuration register. the ISL51002?s internal address pointer auto increments, so to read registers 0x00 through 0x1b, for example, one would write 0x00 in step 2, then repeat step three 28 times, with each read returning the next register value. the ISL51002 has a 7-bit address on the serial bus. the upper 6-bits are permanently set to 100110, with the lower bit determined by the state of pin 67. this allows two ISL51002s to be independently controlled while sharing the same bus. the bus is nominally inactive, with sda and scl high. communication begins when the host issues a start command by taking sda low while scl is high (figure 3). the ISL51002 continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. the host then transmits the 7-bit serial address plus a r/w bit, indicating if the next transaction will be a read (r/w = 1) or a write (r/w = 0). if the address transmitted matches that of any device on the bus, that device must respond with an acknowledge (figure 4). ISL51002
29 fn6164.2 september 19, 2007 once the serial address has been transmitted and acknowledged, one or more bytes of information can be written to or read from the slave. communication with the selected device in the selected direction (read or write) is ended by a stop command, where sda rises while scl is high (figure 3), or a second start command, which is commonly used to reverse data direction without relinquishing the bus. data on the serial bus must be valid for the entire time scl is high (figure 5). to achieve this, data being written to the ISL51002 is latched on a delayed version of the rising edge of scl. scl is delayed and deglitched inside the ISL51002 for three crystal clock periods (120ns for a 25mhz crystal) to eliminate spurious clock pulses that could disrupt serial communication. when the contents of the ISL51002 are being read, the sda line is updated after the falling edge of scl, delayed and deglitched in the same manner. configuration register write figure 6 shows two views of the steps necessary to write one or more words to the configuration register. configuration register read figure 7 shows two views of the steps necessary to read one or more words from the configuration register. scl sda start stop figure 3. valid start and stop conditions scl from host data output from transmitter data output from receiver 8 1 9 start acknowledge figure 4. acknowledge response from receiver scl sda data stable data change data stable figure 5. valid data changes on the sda bus ISL51002
30 fn6164.2 september 19, 2007 ISL51002 serial bus address write this is the 7-bit address of the ISL51002 on the 2-wire bus. the address is 0x98 if pin 67 is low, 0x 9a if pin 67 is high. shift this value left to when adding the r/w bit. d7 d6 d5 d2 d4 d3 d1 d0 a0 a7 a2 a4 a3 a1 ISL51002 register data write(s) this is the data to be written to the ISL51002?s configuration register. note: the ISL51002?s configuration register?s address pointer auto increments after each data write: repeat this step to write multiple sequential bytes of data to the configuration register. a6 a5 1 00 0 1 a ( pin 67) 0 1 r/w ISL51002 register address write this is the address of the ISL51002?s configuration register that the following byte will be written to. ISL51002 serial bus address figure 6. configuration register write start command stop command (repeat if desired) signals the beginning of serial i/o signals the ending of serial i/o s t a r t s t o p data write* register address serial bus address a c k aaaaaaaa a c k dddddddd a c k 100110a0 * the data write step may be repeated to write to the ISL51002?s configuration regist er sequentially, beginning at the register address written in the previous step. sda bus signals from the ISL51002 signals from the host ISL51002
31 fn6164.2 september 19, 2007 figure 7. configuration register read ISL51002 serial bus address write this is the 7-bit address of the ISL51002 on the 2-wire bus. the address is 0x98 if pin 67 is low, 0x9a if pin 67 is high. r/w = 0, indicating next transac tion will be a write. a0 a7 a2 a4 a3 a1 a6 a5 1 00 0 1 a (pin 67) 0 1 r/w ISL51002 register address write this sets the initial address of the ISL51002?s configuration register for subsequent reading. ISL51002 serial bus address start command signals the beginning of serial i/o ISL51002 serial bus address write this is the 7-bit address of the ISL51002 on the 2-wire bus. the address is 0x98 if pin 67 is low, 0x9a if pin 67 is high. r/w = 1, indicating next transacti on(s) will be a read. d7 d6 d5 d2 d4 d3 d1 d0 ISL51002 register data read(s) this is the data read from the ISL51002?s configuration register. note: the ISL51002?s configurati on register?s address pointer auto increments after each data read: repeat this step to read multiple sequential bytes of data from the configuration register. 1 00 0 1 a (pin 67) 1 1 r/w ISL51002 serial bus start command stop command (repeat if desired) ends the previous transaction and starts a new one signals the ending of serial i/o s t a r t s t o p data read* sda bus signals from the ISL51002 signals from the host register address serial bus address a c k aaaaaaaa a c k dddddddd a c k 100110a0 * the data read step may be repeated to read from the ISL51002?s configuration register sequentially, beginning at the register address written in the two steps previous. r e s t a r t serial bus address a c k 100110a1 ISL51002
32 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6164.2 september 19, 2007 ISL51002 metric plastic quad flatpack packages (mqfp) y all around drop in heat spreader 4 stand points exposed pin 1 id d1 d e e1 18.500 ref 12.500 ref c0.600x0.350 (4x) 19.870 0.100 20.000 0.100 (e1) 13.870 0.100 14.000 0.100 a a 1 2 all around (d1) 1 1 section a-a t b b1 t1 ccc c a2 a a1 r0.13 min r0.25 typ c ddd c m l1 0 min 0.200 min t gauge plane detail y 0.13~0.30 128 1 l b e seating plane 0.25 base mdp0055 14x20mm 128 lead mqfp (with and without heat spreader) 3.2mm footprint symbol dimensions ( millimeters) remarks a max 3.40 overall height a1 0.250~0.500 standoff a2 2.750 0.250 package thickness 0~7 foot angle b 0.220 0.050 lead width b1 0.200 0.030 lead base metal width d 17.200 0.250 lead tip to tip d1 14.000 0.100 package length e 23.200 0.250 lead tip to tip e1 20.000 0.100 package width e 0.500 base lead pitch l 0.880 0.150 foot length l1 1.600 ref. lead length t 0.170 0.060 frame thickness t1 0.152 0.040 frame base metal thickness ccc 0.100 foot coplanarity ddd 0.100 foot position rev. 2 2/07 notes: 1. general tolerance: distance 0.100, angle +2.5. 2. matte finish on package body surface except ejection and pin 1 marking (ra 0.8~2.0um). 3. all molded body sharp corner radii unless otherwise specified (max ro.200). 4. package/leadframe misalignment (x, y): max. 0.127 5. top/bottom misalignment (x, y): max. 0.127 6. drawing does not include plastic or metal protrusion or cutting burr. 7. compliant to jedec ms-022. 1 1 1 1 1 2

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